AArch64 MP+dmb.sy+pos-addr-ctrl-ctrlisb-[fr-rf]
"DMB.SYdWW Rfe PosRR DpAddrdR DpCtrldR DpCtrlIsbdR FrLeave RfBack Fre"
Cycle=Rfe PosRR DpAddrdR DpCtrldR DpCtrlIsbdR FrLeave RfBack Fre DMB.SYdWW
Relax=
Safe=Rfe Fre PosRR DMB.SYdWW DpAddrdR DpCtrldR DpCtrlIsbdR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe PosRR DpAddrdR DpCtrldR DpCtrlIsbdR FrLeave RfBack Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X5=z; 1:X7=a; 1:X9=x;
2:X1=x;
}
P0 | P1 | P2 ;
MOV W0,#2 | LDR W0,[X1] | MOV W0,#1 ;
STR W0,[X1] | LDR W2,[X1] | STR W0,[X1] ;
DMB SY | EOR W3,W2,W2 | ;
MOV W2,#1 | LDR W4,[X5,W3,SXTW] | ;
STR W2,[X3] | CBNZ W4,LC00 | ;
| LC00: | ;
| LDR W6,[X7] | ;
| CBNZ W6,LC01 | ;
| LC01: | ;
| ISB | ;
| LDR W8,[X9] | ;
| LDR W10,[X9] | ;
Observed
y=1; x=2; 1:X8=2; 1:X2=0; 1:X10=2; 1:X0=1;
and y=1; x=1; 1:X8=1; 1:X2=0; 1:X10=1; 1:X0=1;